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Cycle Counter for Cortex A8

june
Proposed by Etienne SOBOLE

Permalink of this code :

parse Time:0.000 sec. - count Time:0.000 sec.
Ebola Info Instruction Comment

How to read the cycle counter results

(u.cccc-p ee xx rrr:ll)
  • u is the execution unit. Can be a (arm), n (neon) or v (VPf)
  • cccc is the running cycle
  • p is the pipeline used
  • ee is the number of cycle required by the instruction
  • xx is a lock not due to a register can be
    • p0 wait for arm pipeline 0
    • n0 wait for neon pipeline 0
    • ls wait for load/store functional unit
    • nq wait for NEON queue
    • wb wait for WriteBack when a VMOV Arm reg, Neon reg occured
    • wn wait for NEON empty queue to execute a VPf instruction
  • rrr is the last register that cause a instruction stall
  • ll is the number of "half-cycle" that the instruction have to wait for
Code Registre Alias
R0:
R1:
R2:
R3:
R4:
R5:
R6:
R7: